1. Field of the Invention
The present invention relates to a layout configuration of a semiconductor device, and more particularly, to a configuration of wirings and contacts for providing substrate power supply or normal power supply to a semiconductor device.
2. Description of the Related Art
In recent years, as a semiconductor device has been further miniaturized, an increase in power consumption has become more significant due to an increase in leakage current. Therefore, in order to suppress the increase of the leakage current, the well substrate potential of a semiconductor device is changed to a value that is different from a power supply voltage so that a threshold voltage with respect to the power supply voltage is increased, thereby reducing the leakage current. This is a well-known technique.
Here, a configuration for supplying a potential different from a power supply voltage to a well substrate in a layout configuration of a semiconductor device in which standard cells are arranged side by side, will be described with reference to the following two conventional techniques.
(First Conventional Technique)
FIG. 13A is a plan view showing a layout configuration of a substrate power supply cell 1300 according to a first conventional technique. The substrate power supply cell 1300 has a power supply wiring 1310, a ground wiring 1315, and a substrate power supply wiring 1320. The substrate power supply wiring 1320 is connected to an upper-layer wiring at a substrate power supply connection portion 1330.
FIG. 13B is a cross-sectional view taken along line E-E of FIG. 13A. The power supply wiring 1310 is provided in a layer higher than the substrate power supply wiring 1320. The power supply wiring 1310 is not electrically connected to the substrate power supply wiring 1320 within the substrate power supply cell 1300.
FIG. 14 is a plan view showing a semiconductor device 1400 in which the substrate power supply cell 1300 and standard cells 1410 are arranged. The standard cell 1410 has a power supply wiring 1420, a ground wiring 1425, and a substrate power supply wiring 1430 as in the substrate power supply cell 1300, which are arranged side by side so that their power supply wirings or substrate power supply wirings are connected to each other. The power supply wiring 1420 is connected to the source of a transistor of the standard cell 1410, and the substrate power supply wiring 1430 is connected to the substrate of the transistor of the standard cell 1410. The standard cell 1410 also has at least one pair of input and output terminals. The standard cells 1410 are connected to each other via their input and output terminals. In FIG. 14, an output terminal 1440 and an input terminal 1450 are connected via a wiring and contacts. With this configuration, a potential different from a power supply voltage can be supplied to the substrate, thereby reducing a leakage current (see, for example, Japanese Patent Application Publication No. 2003-309178).
(Second Conventional Technique)
FIG. 15A is a plan view showing a semiconductor device 1500 according to a second conventional technique in which standard cells 1510 are arranged side by side. FIG. 15B is a cross-sectional view taken along F-F of FIG. 15A. Here, a power supply wiring 1520 and a substrate power supply wiring 1530 are connected via a contact 1540 to an upper-layer wiring. The power supply wiring 1520 and the substrate power supply wiring 1530 are also disposed at a boundary between cell rows, and are shared by adjacent standard cells 1510. The power supply wiring 1520 is connected to the source of a transistor of the standard cell 1510, and the substrate power supply wiring 1530 is connected to the substrate of the transistor of the standard cell 1510. With this configuration, a potential different from a power supply voltage can be supplied to the substrate, thereby reducing a leakage current (see, for example, US Patent Application Publication No. 2006/0181309).
The first conventional technique has the following problems. Specifically, the input and output terminals of the standard cell 1410 are disposed between the power supply wiring 1420 and the ground wiring 1425. As shown in FIG. 14, when the output terminal 1440 and the input terminal 1450 of adjacent standard cells are connected, a wiring connecting the output terminal 1440 and the input terminal 1450 needs to make a detour since the substrate power supply connection portion 1330 of the substrate power supply cell 1300 is disposed therebetween, though the output terminal 1440 and the input terminal 1450 have the same wiring track position. The detour wiring may pass through an upper wiring layer using contacts as shown in FIG. 14, or alternatively, may pass through the same wiring layer as shown in FIG. 16. In either case, a wiring resistance increases and therefore a wiring delay increases. In addition, the wiring detour deteriorates wiring efficiency in the vicinity of the substrate power supply cell 1300, leading to an increase in wiring delay of other wirings. If the substrate power supply wiring 1320 has a high resistance, and therefore, the substrate power supply cells 1300 should be spaced from each other by a short distance, the wiring detour frequently occurs, so that the timing design of the semiconductor device is adversely affected.
The second conventional technique has the following problem. Specifically, the power supply wiring 1520 has a narrow width at a connection portion in which the substrate power supply wiring 1530 is connected to the upper-layer wiring. In a miniaturization process, the resistance of the substrate power supply wiring 1530 increases, so that a large number of connection portions in which the substrate power supply wiring 1530 is connected to the upper-layer wiring need to be provided. In this case, the power supply wiring 1520 has a narrow width at a large number of portions. As the number of portions in which the power supply wiring 1520 has a narrow width increases, the wiring resistance of the power supply wiring 1520 increases, so that a voltage drop is more likely to occur during an operation of the semiconductor device, leading to an erroneous operation of the semiconductor device.